Changing the frequency of a polyphase alternating current supply and apparatus therefor

ABSTRACT

A method of and an apparatus for controlling the frequency of a polyphase alternating current supply applied to a polyphase load. SCR&#39;&#39;s or triacs are connected in matrices between each supply phase and each end of each load phase and selected sets thereof are made available for triggering in a predetermined stepping sequence. The current flow in the supply phases is monitored and when current zeros are detected in the supply phases the then available set of SCR&#39;&#39;s or triacs are triggered. If desired, current zeros can be induced in the supply phases. The frequency applied to the load is controllable by varying the rate at which the sets of SCR&#39;&#39;s or triacs are made available for triggering. The effective voltage applied to the load is also controllable by varying the time period between the detection of current zeros and the triggering of the sets of SCR&#39;&#39;s or triacs.

United States Patent 1191 Enslin et al. a

[ CHANGING THE FREQUENCY OF A POLYPHASE ALTERNATING CURRENT SUPPLY AND APPARATUS THEREFOR 1 June 11, 1974 3,678,369 7/1972 Splatt 321/69 R 3,686,558 8/1972 Havas et al. 321/69 R 3,703,672 11/1972 Bird et al......'. 318/227 [75] Inventors: Nicholas Charl de Villiers Enslin, primary p u Newlands; John Austm Charles Attorney, Agent, or Firm-Karl W. Flocks Chapman, Claremont, both of South Af a v 57 ABSTRACT [73] Asslgnee' ggfi gg gg A method of and an apparatus for controlling the frequency of a polyphase alternating current supply ap- Pmvmce South Amca plied to avpolyphase load. SCRs or triacs are con- [22] Filed: Sept. 20, 1972 nected in matrices between each supp] phase and h d f h l d h d 1 d h f eac en 0 eac 0a p ase an se ecte sets t ereo [21] Appl' 290470 are made available for triggering in a predetermined stepping sequence. The current flow in the supply [30] Foreign Application Priority Data phases is monitored and when current zeros are de- 0m. 7, 1971 South Africa 71/6729 tected in the p y Phases the then available Set of SCRs or triacs are triggered. If desired, current zeros 52 us. c1 321/61, 318/227, 318/231 can vbe induced in the p y p The frequency 51] 1.11.0. H02m 5/30 pp to aha load is aaaarallabla y varying the rate 5 Field f Search 31 /227 231; 321/ 1 9 at which the sets of SCRs or triacs are made available 323 3 24 for triggering. The effective voltage applied to the g load is also controllable by varying the time period be- 5 R f en i tween the detection of current zeros and the triggering Of the Sets Of SCR,S or triacs.

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PATENTEBMH m4 3l816l808 sum 8 or 22 XI X2 T- lOV L K: Em I mg CHANGING THE FREQUENCY OF A POL YPHASE ALTERNATING CURRENT SUPPLY AND APPARATUS THEREFOR This invention relates to the changing of the frequency of a polyphase alternating current supply and to apparatus therefor. In particular, it relates to a frequency changer suitable for use with synchronous and asynchronous alternating current motors.

In accordance with the invention a method of controlling the frequency of a polyphase alternating current supply applied to a polyphase load includes connecting'an SCR or Triac Matrix between each supply phase and each end of each load phase;

making selected sets of SCRs or Triacs in the matrices available for triggering in a predetermined cyclic stepping sequence;'and

monitoring current flow in the supply phases to detect current zeros in the supply'phases and triggering the then available set of SCRs or Triacs in the matrices when current zeros are detected.

Further according to the invention there is provided a frequency changer for controlling the frequency of a polyphase alternating current supply applied to a polyphase load, which includes an SCR or Triac matrix connectable between each supply phase and'each end of each load phase;

monitoring means for detecting current zeros in the supply phases; and

electrical degrees relative to the supply phases. Dependent on when current zeros occur, the sets of SCRs or control means adapted to make selected sets of SCRs or triacs in the matrices available for triggering in a predetermined cyclic stepping sequence and the control means being responsive to the monitoring means to trigger the then available set of SCRs or triacs when current zeros are detected in the supply phases by the monitoring means.

Thus dependent on when the current zeros occur the set of SCRs or triacs then available in the stepping sequence will be triggered. It will be appreciated that in each cycle, not every set of SCRs ortriacs need be triggered by only those sets available for triggering when current zeros do occur.

The method may further include selectively inductv ing current zeros in the supply phases, commutation.

The frequency changer may thus include inhibiting means connectable in series with at least one of the supply phases and operable to induce current zeros in a particular supply phase.

The rate at which the sets of SCRs or triacs are made available for triggering in succession may be adjustably variable. In this manner the output frequency applied to the load can be varied.

The time period between the detection of the current zeros in the supply phases and the triggering of the then available set of SCRs or triacs may be controllably varied. This permits variation of the effective voltage applied to the load. Conveniently, a delay unit may be provided intermediate the monitoring means and the control means for controllably delaying the time period between the detection of the current zeros and the triggering of the sets of SCRs or triacs. The delay unit may then be adjustably variable to permit variation of the said time period.

When controlling the frequency of a three phase alternating current supply, the sets of SCRs or triacs may be .made available for triggering in fixed steps of sixty e.g. by forced triacs may only be triggered in multiples of steps of 60 electrical degrees.

The control means may include a stepping unit e.g. in the form of a ring counter for making the sets of SCRs or triacs in the matrices successively available for triggering. By adjusting the rate of operation of the stepping unit, the output frequency of the apparatus can be controllably varied.

A plurality of trigger circuits responsive to the control means may be provided for triggering the various sets of the SCRs or triacs. The trigger circuits may be connected to the control means via a decoding matrix and a buffer amplifier provided intermediate the stepping unit and the trigger circuits.

An embodiment of a frequency changer in accordance with the invention used in conjunction with a three phase motor is now described by way of example with reference to the accompanying drawings in which:

FIG. 1 shows a phasor diagram of the relationship in time of the supply phases applied to the frequency changer in accordance with the invention;

FIG. 2 shows a phasor diagram of the relationship in time of the derived phases emitted by the frequency changer in accordance with the invention;

FIG. 3 shows a table indicating the steps in which the supply phases are stepped and applied to the windings A, B and C of a three phase motor;

FIG. 4 shows a schematic block diagram of a frequency changer in accordance with the invention;

FIG. 5 shows a schematic circuit diagram of a master oscillator used in the frequency changer shown in FIG.

FIG. 6 shows a schematic circuit diagram of a stepping unit used for stepping the frequency changer shown in FIG. 4;

FIG. 7 shows a schematic circuit diagram of gating means used in the frequency changer shown in FIG. 4;

FIG. 8 shows a schematic circuit diagram of a decoding matrix and buffer amplifier circuit used in the frequency changer shown in FIG. 4;

FIG. 8a shows in table form the relationship between the inputs and outputs of the decoding matrix and buffer amplifier shown in FIG. 8;

FIG. 9 shows a schematic circuit diagram of portion of a trigger circuit used for controlling the SCRs or triacs in the frequency changer shown in FIG. 4;

FIG. 10 shows an SCR matrix used in the frequency changer shown in FIG. 4;

FIG. 11 shows a schematic circuit diagram of a current detector used for detecting current zeros in the Referring to FIG. 1, the three supply phases designated Red (R), Yellow (Y) and Blue (B) are shown. The phases are in the normal manner displaced by degrees in time fromone another.

, pleted. I

In FIG. 2, the derived phases obtained from the frequency changerare shown as applied to the windings A, B and C of a motor. Each derived phase is, as shown, available in steps of 60 electrical degrees relative to the supply phases. In FIG. 3, the various steps in whichthe derived phases are applied to the windings A, B and C of a motor are shown. In this system, six steps are possible at intervals of 60 electrical degrees. The six types of connections are'respectively referenced (i) to (vi). During the firststep, the SCR or triac matrices are triggered so that the red and yellow phases are connected to winding A, the yellow and blue phases are connected to winding B, and the blue and red phases are connected to winding C; Similarly, in the second step, the red and blue phases are connected to winding A, the yellow and red phases are connected to winding B; and the blue and yellow phases are connected to winding C, and so on. Aswill be appreciated, the fourth, fifth and sixth steps are similar to the first, second and third steps respectively, except that the connections are reversed on each winding. Thus whereas in the first step, the red and yellow phases are-connected to winding A, in the direction of red to yellow, in the fourth step the yellow and red phases are connected to winding A in. the direction yellowto red. The six steps are available for selection in thesequence shown in the table, the first step being available after the sixth step of the cycle is com- Referring now to FIG. 4, a block diagram of the frequency changer generally designated by a reference numeral is shown. The frequency changer includes three SCR or triac matrices generally indicated by a reference numeral 12. Matrix A is connected to both ends of winding A, matrix B to both ends of winging B and matrix C to both ends of winding C, of a three phase motor (not shown). As is more clearly indicated in FIG. 10, a matrix is connected between eachbad phase R, Y, and B of the supply 14 and each end 0 each load winding A, B and C of the motor.

The triggering of selected sets of SCRs or triacs in thematrices 12 is accomplished by a plurality of trigger circuits 16(which are more clearly shown in FIG.'9). The control means includes gating means including AND gates 18 and a latch;20, both of which are shown in detail in FIG. 7.

The control means also includes a stepping unit in the form of a six stage ring counter 22 (details of which are shown in FIG. '6). A decoding matrix and buffer amplifier circuit 24 (details of which are shown in FIG. 8) and a master oscillator 26 (details of which are shown in FIG. 5) are provided intermediate the ring counter 22 and the trigger circuits 16.

Monitoring means are provided in theform of three current detector circuits 28. Each of the supply phases R, Y and Bare connected in series with one of the three current detector circuits 28. Details of the current detectors are shown in FIG. 11. t i

The red and yellow phases are connected to the SCR or triac matrices 12 via inhibiting means in the form of forced commutation circuits 30. (details of which are shown in FIG. 13) for inducing forced commutation in these two supply phases. I

The current detectors 28 control the latch and thus the gating means 18 via a logic detection unit and delay circuit 32 (details of which are shown in FIG. 12). The logic detection unit 32.1 is in the form of an AND gate by means of which the outputs of the current detectors 28 are ANDED. The delay circuit 32.2 is made adjustable in order that the period after which the latch 20 is unset when current zeros occur may be varied.

The operation of the frequency changer shown in FIG. 4 is as follows. The master oscillator 26 emits pulses to the six stage ring counter 22. On each step of the ring counter 22, selected sets of the trigger circuits 16 can be made operative via the decoding matrix and buffer amplifier circuit 24 so that selected sets of SCRs ortriacs in the matrices 12 are available for triggerin in the stepping sequence shown in FIG. 3.

The master oscillator 26 also emits pulses to the latch 20 to set it. When the latch 20 is set, an inhibit gating pulse is applied to the AND gates 18 thereby preventing the triggering of the sets of SCRs or triacs in the matrices 12. When the latch20 is set, the gating signal applied to the preceding set of SCRs or triacs which were triggered while the latch 20 was unset, is also removed. I I

However as SCRs or triacs do not extinguish merely because of the removal of the gating signal, the triggered SCRs or triacs will remain ON until the current in the phases goes to zero. Natural line current zeros will occur'after there has been a reversal of current flow in any two of the three phases.

Ignoring the forced commutation circuit 30 for the time being, assume that the ringcounter 22 is on the sixth step and has notyet been moved onto the first 1 step. The latch 20 would have been set at the beginning of the 6th step. Assume, however, that the latch has been reset by the detection of current zeros some time beforethe ring counter moves onto its first step.

When the latch 22 is reset, the SCRs or triacs corresponding to the sixth step will be triggeredand will remain ON until the line current in the supply phases goes to zero.

When the ring counter 22 is moved to its first step by a pulse from the master oscillator 26, the latch 20 is simultaneously set and the AND gates 18 are inhibited to prevent further sets of SCRs or triacs beingtriggered. The'SCRs or triacs triggered on the 6th step may however still be ONprovided no natural current zeros have occurred in the interim period. If current zeros now occur and the delay provided by the delay unit 32.2 is such that the latch 20 is reset before the beginning of the second step, then the first set of SCRs or triacs will be triggered.

If, however, current zeros only occur after the beginning of the second step, or the delay provided by the delay unit 32.2 is such that the latch 20 is reset after the beginning of the second step, then the SCRs or triacs corresponding to the first step will not be triggered and the SCRs or triacs of the second step will be triggered. Any number of steps can be skipped in this fashion dependent on when current zeros occur.

Thus, while current flows in the supply phases 14, the latch 20 remins set. While the latch 20 is set, the previously triggered set of SCRs or triacs will remain triggered until current zeros occur when they will extinguish naturally. Successive sets of SCRs or triacs are prevented from being triggered by the latch 20 inhibiting AND gates 18. In the meantime, the ring counter 22 may have been stepped up to any one of its six steps. When current zeros do occur, the latch 20 is unset thereby causing another particularset of SCRs or triacs to be triggered, the particular set being dependent on which step the ring counter 22 is on.

By varying the output frequency of the oscillator 26 to vary the rate at which the ring counter is stepped, it will be appreciated that selected sets of SCRs will be triggered in sequence in each cycle. For example, with a particular setting of the frequency of the master oscillator 26, in every cycle, the selected sets of SCRls or triacs of steps (i), (iii) and (v) may be triggered, the selected sets of SCRs or triacs of steps (ii), (iv) and (vi) being inoperative, that is these steps are skipped. As the frequency of the master oscillator 26 is increased, more steps in each cycle will be skipped and be inoperative.

By varying the delay in the variable delay circuit 32.2, in each cycle, the time period between the detection of the current zeros and the triggering of the then available set of SCRs or triacs can be varied. This permits adjustment of the effective voltage applied to the motor windings.

The above operation. has been described whereby natural'current zeros occurring in the supply phases 14 are used to control the triggering of the sets of SCRs or triacs. By connecting the forced commutation circuit 30 in series with two of the supply phases as shown in FIG. 4, current zeros can be induced in the supply phases.

The operation of the frequency changer shown in FIG. 4, with the forced. commutation circuit 30 in cluded will now be described. Assume that the first clock pulse from the oscillator 26, moves the ring counter to position 1, and sets the latch 20, preventing any SCRs from being triggered. The clock pulse also operates the commutation circuit 30 to force the line current in the red and yellow phases to go to zero, and hence-in the blue phase as there is no neutral connection. Thus, shortly after the occurrence of a clock pulse, all the currents will be zero and the logic detection unit 32.] will give an output. This will then initiate the delay unit 32.2. Assume that the delay unit 32.2 is set to delay the signal for one and a half clock pulses. Thus, the latch 20 will remain in the inhibit mode between the first and second clock pulses, thus preventing any SCRs from firing. The current will thus remain at zero, and reactivation of the commutation circuit 30 by the second clock pulse will have no effect. The only effect the second clock pulse will have, is to move the ring counter 22 to its second position.

Midway between the second and .third pulses, the delay unit 32.2 will emit a pulse. This pulse will then unset the latch 20, and result in the SCRs corresponding to position 2 of the ring counter 22 being fired. Current will then flow through the circuit as the commutation circuit 30 only blocks current flow for the duration of the clock pulse, until the third clock pulseactivates the commutation circuit 30 (forcing the currents to zero), resets the latch 20 to the inhibit mode, and moves the ring counter 22 to the third position. As the latch 20 is in the inhibit mode, the SCRs corresponding to the third position will not fire. I-Iowever, as the delay unit 32.2 is set for a delay of one and a half periods, after the fourth clock pulse, the SCRs corresponding to the fourth position of the ring counter 22, will be tired, thus allowing current to flow. This current flow will be extinguished by the fifth clock pulse.

If the delay unit 32.2 is now changed to delay for less than one period, the delay unit 32.2 will emit a pulse prior to the sixth clock pulse. The SCRs corresponding to the fifth position will therefore be fired, allowing current to flow in the circuits for a short period, till the advent of the sixth clock pulse, whereafter the current will be extinguished.

The various portions of the frequency changer shown in FIG. 4 will now be described with reference to FIGS. 5 to 13.

Referring to FIG. 5, the master oscillator 26 is shown. This circuit comprises a unijunction oscillator 26.1 and two transistor stages 26.2 and 26.3. An output 26.4 is taken from the transistor stage 26.2 to the latch 20 of FIG. 4 and an output 26.5 is taken from the transistor stage 26.3 to the ring counter 22 and the forced commutation circuits 30 of FIG. 4.

The frequency of the master oscillator 26 is controlled by a variable resistor 26.6 and by a switch 26.7 which connects one of two difference capacitors 26.8 or 26.9 in circuit to control the frequency over a range from 0 to 300 Hz.

Referring now to FIG. 6, the ring counter 22 is shown which is made of standard integrated circuits. For every pulse applied from the oscillator 26 on an input line 22.], the ring counter is stepped up one position and its outputs 22.2 are successively operative.

In FIG. 7, the latch 20 and AND gates 18 are shown. The latch 20 has an input 20.1 from the oscillator 26 to set it and an input 20.2 from the current detectors 28 via the summing unit 32.1 and delay circuit 32.2 to unset it. The output of the latch 20 is connected via a line 20.3 to one input of each of the AND gates 18. Each of the AND gates 18 are identical. The other inputs to the respective AND gates 18 are obtained from the ring counter 22 via input connections 18.1. The outputs of each of the AND gates are provided on output connections 18.2.

Thus, when the latch 20 is set, all the AND gates 18 are inhibited. Only when the latch 20 is unset thereby removing the inhibit signal, will the ring counter 22 be able to trigger the then available set of SCRs or triacs.

Referring now to FIG. 8, the decoding matrix and buffer amplifier circuit 24 is shown. The inputs collectively referenced 24.1 comprise six inputs corresponding to the sixsteps of the ring counter 22, and cause outputs collectively referenced 24.2 as shown in the table given in FIG. 8a.

Thus, when the ring counter 22 is on its first step, an input on position 1 of the inputs 24.1 will cause an output on positions 1 and 6 of the outputs 24.2, and so on.

Referring to FIG. 9, portion of the trigger circuits 16 is shown. The trigger circuits 16 comprise a multivibrator oscillator 16.1 which feeds twelve similar amplifiers, one of which is shown at 16.2. There are twelve such amplifiers for each of the three matrices 12.

The output of the multivibrator oscillator 16.1 is taken from two leads 16.3 and fed to each of the amplifiers 16.2 in parallel via input connections 16.4. Each amplifier 16.2 also includes an isolating transformer 16.5 which is connected to a selected SCR or triac in the matrices 12 via two output connections 16.6. Each amplifier 16.2 also has a controlling input from the decoding matrix and buffer amplifier 24 connected to connection 16.7, there being two amplifiers 16.2 connected to each of the outputs 24.2 of the amplifiers 24 (FIG. 8).

triac matrices 12 is shown," the three matrices being similar. In this embodiment, SCRs are shown in place of triacs, the SCRs being connected in anti-parallel relationship in series with each end of each motor windincreased from zero cycles per second to 300 cycles per second, more of the steps in the cycle of steps shown ing. There is one pair of SCRs connected between each supply phase and each end of each motor winding. The outputs 16.6 of the amplifiers 16.2 (FIG. 9) are connected across the gate and cathode electrodes of the SCRs as shown, each pair of amplifiers 16.2 controlling the triggering of one pair of anti-parallel connected SCRs. If triacs are used, the number of trigger circuits 16 can be halved.

Referring to FIG. 11, a'current detector 28 is shown. Only one of the current detectors connectedin series with one of the supply phases has been shown, the other two being identical. The line current in the supply phases is detected as a voltage across two anti-parallel connected power'diodes 28.1 of low-voltage but high current rating. This detected voltage is adapted to inhibit the output from a multivibrator 28.2 to provide a zero output on lines 28.3 whenever current in the supply lines is not at zero. When the line current in the supply phases falls to zero, the inhibit signal applied to the multivibrator 28.2 is removed and a DC signal is developed at output terminal 28.3 The outputs 28.3 of each current detector 28 are connected to the logic detection unit 32.1. v A

Referring now to FIG. 12, the logic detection unit and delay circuit 32.are'shown. The inputs from the current detectors 28 are applied on lines 32.3 to the logic detection unit 32.1 and when all the current detectors 28 yield the DC signal indicating that current zeros are present and that the previously triggered SCRs or triacs have, extinguished, an output is provided on line 32.4 via a NAND gate 32.5 after a period dependent upon the setting of the delay circuit 32.2 A

minimum delay is provided to ensure that all the SCRs I or triacs have extinguished fully and that a full recovery of voltage blocking capability has been attained. The delay is variable by adjusting resistor 32.6. Referring now to FIG. 13, the forced commutationcircuit is shown. A circuit as shownin FIG. 13 is connected in series with each of the red and yellowphases of the sup- .ply. The circuit includes a power transistor 30.1 in a bridge connection. The power transistor 30.1 is controlled by the output from a multivibrator 30.2. The

multivibrator 30.2 is gated when a control signal from the master oscillator 26 is applied to a line 30.3. When a pulse is received from the master oscillator 26 on the line 30.3, the result is that the power transistor 30.1 is cut off thereby blocking that particular phase to the motor windings and causing current zeros in that phase. When the pulse ceases, the multivibrator 30.2 is no longer gated and again pulses the power transistor 30.1 which no longer blocks that phase and allows current to flow if the relevant SCRs are switches on.

It is also possible to use SCRs in place of the power v transistor 30.1, in which case, the SCRs have to be force-commutated with the aid of reactors and capacitors.

With a frequency changer as described the speed of a three phase motor can be varied from above synchronous speed to standstill in both directions of rotation. The output frequency of the frequency changer depends upon the output frequency ofthe master oscillator 26. As the frequency of the master oscillator 26 is in FIG. 3 will be skipped thereby reducing the speed of the motor.

We claim:

1. A method of controlling the frequency of a polyphase alternating current supply applied to a polyphase load which includes connecting an SCR or Triac Matrix between each supply phase and-each end of each load phase; making selected sets of SCRs or triacs in the matrices available for triggering in a predetermined cy- ,clic stepping'sequence; and i monitoring current flow in the supply phases to detect current-zeros inthe supply phases and triggering the then available set of SCRs or triacs in the t, matrices in a time period after the detection of said current zeros.

2. A method as claimed in claim 1, which further includes selectively-inducing current zeros in the supply phases. A

3. A method as claimed in claim 1 in which the rate at which the sets of-SCRs or triacs are made available for triggering in succession is adjustably variable.

4. A method as claimed in claim 1, which further includes controllably varying the time period between the detection of the current zeros in the supply phases and the triggering of the then available set of SCRs or triacs.

5. A method as claimed in claim 1, for controlling the frequency of a three phase alternating current supply, in which the sets of SCRsor triacs are made available for triggering in fixed steps of sixty. electrical degree relative to the supply-phases. Y

6. A frequency changer for controlling the frequency of a polyphase alternating current supply applied to a polyphase load, which includes an SCR or triac matrix connectable between each supply phase and each end of each load phase; monitoring means for detecting current zeros in the supply phases; and control means adapted to make selected sets of SCRs or triacs in the matrices available for triggering in a predetermined cyclic stepping sequence and the control means being responsive to the monitoring means to trigger the then available set of SCRs or triacs when current zeros are detected in the supply phases by the monitoring means. 7. A frequency changer as claimed in claim 6, which further includes inhibiting means connectable in series with at least one of the supply phases and operable to induce current zeros in a particular supply phase.

8. Afrequency changer as claimed in claim 6,.which further includes a delay unit intermediate the monitoring means and the-control means for controllably delaying the time period between the detection of the current zeros and the triggering of the sets of SCRs or triacs.

9. A frequency changer as claimed in claim 8, in

which the delay unit is adjustably variable to permit 

1. A method of controlling the frequency of a polyphase alternating current supply applied to a polyphase load which includes connecting an SCR or Triac Matrix between each supply phase and each end of each load phase; making selected sets of SCR''s or triacs in the matrices available for triggering in a predetermined cyclic stepping sequence; and monitoring current flow in the supply phases to detect current zeros in the supply phases and triggering the then available set of SCR''s or triacs in the matrices in a time period after the detection of said current zeros.
 2. A method as claimed in claim 1, which further includes selectively inducing current zeros in the supply phases.
 3. A method as claimed in claim 1 in which the rate at which the sets of SCR''s or triacs are made available for triggering in succession is adjustably variable.
 4. A method as claimed in claim 1, which further includes controllably varying the time period between the detection of the current zeros in the supply phases and the triggering of the then available set of SCR''s or triacs.
 5. A method as claimed in claim 1, for controlling the frequency of a three phase alternating current supply, in which the sets of SCR''s or triacs are made available for triggering in fixed steps of sixty electrical degrees relative to the supply phases.
 6. A frequency changer for controlling the frequency of a polyphase alternating current supply applied to a polyphase load, which includes an SCR or triac matrix connectable between each supply phase and each end of each load phase; monitoring means for detecting current zeros in the supply phases; and control means adapted to make selected sets of SCR''s or triacs in the matrices available for triggering in a predetermined cyclic stepping sequence and the control means being responsive to the monitoring means to trigger the then available set of SCR''s or triacs when current zeros are detected in the supply phases by the monitoring means.
 7. A frequency changer as claimed in claim 6, which further includes inhibiting means connectable in series with at least one of the supply phases and operable to induce current zeros in a particular supply phase.
 8. A frequency changer as claimed in claim 6, which further includes a delay unit intermediate the monitoring means and the control means for controllably delaying the time period between the detection of the current zeros and the triggering of the sets of SCR''s or triacs.
 9. A frequency changer as claimed in claim 8, in which the delay unit is adjustably variable to permit variation of the said time period.
 10. A frequency changer as claimed in claim 6, in which the control means includes a stepping unit for making the sets of SCR''s or triacs in the matrices successively available for triggering.
 11. A frequency changer as claimed in claim 10, in which the stepping unit is adjustable to permit adjustment of the rate at which the sets of SCR''s or triacs are made available for triggering. 